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typical connection features ? floating channel designed for bootstrap operation fully operational to +1200v tolerant to negative transient voltage dv/dt immune ? gate drive supply range from 12 to 20v ? undervoltage lockout for both channels ? 3.3v logic compatible separate logic supply range from 3.3v to 20v logic and power ground 5v offset ? cmos schmitt-triggered inputs with pull-down ? cycle by cycle edge-triggered shutdown logic ? matched propagation delay for both channels ? outputs in phase with inputs ? also available lead-free (pbf) description the ir2213(s) is a high voltage, high speed power mosfet and igbt driver with independent high and low side referenced output channels. proprietary hvic and latch immune cmos technologies enable ruggedized monolithic construction. logic inputs are compatible with standard cmos or lsttl outputs, down to 3.3v logic. the output drivers feature a high packages ir2213(s) & (pbf) high and low side driver product summary v offset 1200v max. i o +/- 1.7a / 2a v out 12 - 20v t on/off (typ.) 280 & 225 ns delay matching 30 ns 16-lead soic (wide body) 14-lead pdip preliminary data sheet no. pd60030 rev.p pulse current buffer stage designed for minimum driver cross-conduction. propagation delays are matched to simplify use in high frequency applications. the floating channel can be used to drive an n- channel power mosfet or igbt in the high side configuration which operates up to 1200 volts. www.irf.com 1 (refer to lead assignments for correct pin configuration). this/these diagram(s) show electrical connections only. please refer to our application notes and designtips for proper circuit board layout.
2 www.irf.com ir2213( s ) & (pbf) symbol definition min. max. units v b high side floating supply voltage -0.3 1225 v s high side floating supply offset voltage v b - 25 v b + 0.3 v ho high side floating output voltage v s - 0.3 v b + 0.3 v cc low side fixed supply voltage -0.3 25 v lo low side output voltage -0.3 v cc + 0.3 v dd logic supply voltage -0.3 v ss + 25 v ss logic supply offset voltage v cc - 25 v cc + 0.3 v in logic input voltage (hin, lin & sd) v ss - 0.3 v dd + 0.3 dv s /dt allowable offset supply voltage transient (figure 2) ? 50 v/ns p d package power dissipation @ t a +25c (14 lead pdip) ? 1.6 (16 lead soic) ? 1.25 r thja thermal resistance, junction to ambient (14 lead pdip) ? 75 (16 lead soic) ? 100 t j junction temperature ? 125 t s storage temperature -55 150 t l lead temperature (soldering, 10 seconds) ? 300 symbol definition min. max. units v b high side floating supply absolute voltage v s + 12 v s + 20 v s high side floating supply offset voltage note 1 1200 v ho high side floating output voltage v s v b v cc low side fixed supply voltage 12 20 v lo low side output voltage 0 v cc v dd logic supply voltage v ss + 3 v ss + 20 v ss logic supply offset voltage -5 (note 2) 5 v in logic input voltage (hin, lin & sd) v ss v dd absolute maximum ratings absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. all voltage param- eters are absolute voltages referenced to com. the thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. recommended operating conditions the input/output logic timing diagram is shown in figure 1. for proper operation the device should be used within the recommended conditions. the v s and v ss offset ratings are tested with all supplies biased at 15v differential. note 1: logic operational for v s of -5 to +1200v. logic state held for v s of -5v to -v bs . (please refer to the design tip dt97-3 for more details). note 2: when v dd <5v, the minimum v ss offset is limited to -v dd c/w w v v c
ir2213( s ) & (pbf) www.irf.com 3 symbol definition min. t yp. max. units test conditions t on turn-on propagation delay ? 280 ? v s = 0v t off turn-off propagation delay ? 225 ? v s = 1200v t sd shutdown propagation delay ? 230 ? v s = 1200v t r turn-on rise time ? 25 ? t f turn-off fall time ? 17 ? mt delay matching, hs & ls turn-on/off ? ? 30 ns dynamic electrical characteristics v bias (v cc , v bs , v dd ) = 15v, c l = 1000 pf, t a = 25 c and v ss = com unless otherwise specified. the dynamic electrical characteristics are measured using the test circuit shown in figure 3. symbol definition min. t yp. max. units test conditions v ih logic ?1? input voltage 9.5 ? ? v il logic ?0? input voltage ? ? 6.0 v oh high level output voltage, v bias - v o ? ? 1.2 i o = 0a v ol low level output voltage, v o ? ? 0.1 i o = 0a i lk offset supply leakage current ? ? 50 v b = v s = 1200v i qbs quiescent v bs supply current ? 125 230 v in = 0v or v dd i qcc quiescent v cc supply current ? 180 340 v in = 0v or v dd i qdd quiescent v dd supply current ? 15 30 v in = 0v or v dd i in+ logic ?1? input bias current ? 20 40 v in = v dd i in- logic ?0? input bias current ? ? 1.0 v in = 0v v bsuv+ v bs supply undervoltage positive going 8.7 10.2 11.7 threshold v bsuv- v bs supply undervoltage negative going 7.9 9.3 10.7 threshold v ccuv+ v cc supply undervoltage positive going 8.7 10.2 11.7 threshold v ccuv- v cc supply undervoltage negative going 7.9 9.3 10.7 threshold i o+ output high short circuit pulsed current 1.7 2.0` ? v o = 0v, v in = v dd pw 10 s i o- output low short circuit pulsed current 2.0 2.5 ? v o = 15v, v in = 0v pw 10 s a v a v static electrical characteristics v bias (v cc , v bs , v dd ) = 15v, t a = 25 c and v ss = com unless otherwise specified. the v in , v th and i in parameters are referenced to v ss and are applicable to all three logic input leads: hin, lin and sd. the v o and i o parameters are referenced to com and are applicable to the respective output leads: ho or lo.
4 www.irf.com ir2213( s ) & (pbf) symbol description v dd logic supply hin logic input for high side gate driver output (ho), in phase sd logic input for shutdown lin logic input for low side gate driver output (lo), in phase v ss logic ground v b high side floating supply ho high side gate drive output v s high side floating supply return v cc low side supply lo low side gate drive output com low side return functional block diagram lead definitions lead assignments 14 lead pdip 16 lead soic (wide body) ir 2213 ir2213s part number
ir2213( s ) & (pbf) www.irf.com 5 figure 1. input/output timing diagram figure 2. floating supply voltage transient test circuit figure 3. switching time test circuit figure 4. switching time waveform definition figure 6. delay matching waveform definitions ! " "" #$ #$ %$ %$ $ $ #$ #$ $ %$ (0 to 1200v) figure 5. shutdown waveform definitions sd t sd ho lo 50% 90% hv =10 to 1200v <50 v/ns
6 www.irf.com ir2213( s ) & (pbf) figure 12a. logic ?1? input threshold vs. temperature figure 12b. logic ?1? input threshold vs. voltage figure 10a. turn-on rise time vs. temperature figure 11a. turn-off fall time vs. temperature figure 11b. turn-off fall time vs. voltage figure 10b. turn-on rise time vs. voltage 0 20 40 60 80 100 -50 -25 0 25 50 75 100 125 temperature (c) turn-on rise time (ns) max. typ. 0 20 40 60 80 100 10 12 14 16 18 20 v bias supply voltage (v) turn-on rise time (ns) max. typ. 0 10 20 30 40 50 -50 -25 0 25 50 75 100 125 temperature (c) turn-off fall time (ns) max. typ. 0 10 20 30 40 50 10 12 14 16 18 20 v bias supply voltage (v) turn-off fall time (ns) max. typ. 0.0 3.0 6.0 9.0 12.0 15.0 -50 -25 0 25 50 75 100 125 temperature (c) logic "1" input threshold (v) min. logic ' 1' input threshold (v) 0 3 6 9 12 15 0 2 4 6 8 10 12 14 16 18 20 max. v dd logic supply voltage (v)
ir2213( s ) & (pbf) www.irf.com 7 figure 13a. logic ?0? input threshold vs. temperature figure 13b. logic ?0? input threshold vs. voltage figure 14a. high level output vs. temperature figure 14b. high level output vs. voltage figure 15b. low level output vs. voltage figure 15a. low level output vs. temperature 0.0 3.0 6.0 9.0 12.0 15.0 -50 -25 0 25 50 75 100 125 temperature (c) logic "0" input threshold (v) max. 0.00 1.00 2.00 3.00 4.00 5.00 -50 -25 0 25 50 75 100 125 temperature (c) high level output voltage (v) max. 0.00 0.20 0.40 0.60 0.80 1.00 -50 -25 0 25 50 75 100 125 temperature (c) low level output voltage (v) max. 0.00 1.00 2.00 3.00 4.00 5.00 10 12 14 16 18 20 v bias supply voltage (v) high level output voltage (v) m ax. 0.00 0.20 0.40 0.60 0.80 1.00 10 12 14 16 18 20 v bias supply voltage (v) low level output voltage (v) m ax. 0 3 6 9 12 15 02468101214161820 min . logic '0' input threshold (v) v dd logic supply voltage (v)
8 www.irf.com ir2213( s ) & (pbf) figure 16b. offset supply current vs. voltage figure 16a. offset supply current vs. temperature figure 18a. v cc supply current vs. temperature figure 18b. v cc supply current vs. voltage figure 17a. v bs supply current vs. temperature figure 17b. v bs supply current vs. voltage 0 125 250 375 500 625 10 12 14 16 18 20 v cc fixed supply voltage (v) v cc supply current (a) max. typ. 0 125 250 375 500 625 -50 -25 0 25 50 75 100 125 temperature (c) v cc supply current (a) max. typ. 0 100 200 300 400 500 -50 -25 0 25 50 75 100 125 temperature (c) v bs supply current (a) max. typ. 0 100 200 300 400 500 10 12 14 16 18 20 v bs floating supply voltage (v) v bs supply current (a) max. typ. 0 100 200 300 400 500 offset supply leakage current (a) max. 0 100 200 300 400 500 -50 -25 0 25 50 75 100 125 temperature (c) offset supply leakage current (a) max. v b boost voltage (v) 0 200 400 600 800 1000 1200
ir2213( s ) & (pbf) www.irf.com 9 figure 21a. logic ?0? input current vs. temperature figure 19a. v dd supply current vs. temperature figure 20a. logic ?1? input current vs. temperature 0 20 40 60 80 100 -50 -25 0 25 50 75 100 125 temperature (c) v dd supply current (a) max. typ. 0 20 40 60 80 100 -50 -25 0 25 50 75 100 125 temperature (c) logic "1" input bias current (a) max. typ. 0.00 1.00 2.00 3.00 4.00 5.00 -50 -25 0 25 50 75 100 125 temperature (c) logic "0" input bias current (a) max. v dd supply current ( a) figure 19b. v dd supply current vs. v dd voltage 0 10 20 30 40 50 60 02468101214161820 v dd logic supply voltage (v) figure 20b. logic ?1? input current vs. v dd voltage logic ?1? input bias current ( a) v dd logic supply voltage (v) 0 10 20 30 40 50 60 0 2 4 6 8 10 12 14 16 18 20 figure 21b. logic ?0? input current vs. v dd voltage logic ?0? input bias current ( a) v dd logic supply voltage (v) 0 1 2 3 4 5 02468101214161820 max max max typ. typ.
10 www.irf.com ir2213( s ) & (pbf) figure 22. maximum v s negative offset vs. v bs supply voltage figure 23. maximum v ss positive offset vs. v cc supply voltage 0.0 4.0 8.0 12.0 16.0 20.0 10 12 14 16 18 20 v cc fixed supply voltage (v) v ss logic supply offset voltage (v) typ. -15.0 -12.0 -9.0 -6.0 -3.0 0.0 10 12 14 16 18 20 v bs floating supply voltage (v) v s offset supply voltage (v) typ. 0v 1 00v 200v 300v 15 25 35 45 55 65 0.1 1 10 100 frequency (khz) temperature ( o c) 0v 1 00v 200v 300v 15 25 35 45 55 65 0.1 1 10 100 frequency (khz) temperature ( o c) figure 24. ir2213s vs. frequency (irfbc20) r gate =33 , v cc =15v figure 25. ir2213s vs. frequency (irfbc30) r gate =22 , v cc =15v
ir2213( s ) & (pbf) www.irf.com 11 0v 100v 200v 300v 15 25 35 45 55 65 75 0.1 1 10 100 frequency (khz) temperature ( o c) 0v 100v 200v 300v 15 25 35 45 55 65 75 0.1 1 10 100 frequency (khz) temperature ( o c) 0v 100v 200v 300v 15 25 35 45 55 65 0.1 1 10 100 frequency (khz) temperature ( o c) 300v 200v 100v 0v 15 25 35 45 55 65 0.1 1 10 100 frequency (khz) temperature ( o c) figure 27. ir2213s vs. frequency (irfbc50) r gate =10 , v cc =15v figure 28. ir2213 vs. frequency (irfbc20) r gate =33 , v cc =15v figure 29. ir2213 vs. frequency (irfbc30) r gate =22 , v cc =15v figure 26. ir2213s vs. frequency (irfbc40) r gate =15 , v cc =15v
12 www.irf.com ir2213( s ) & (pbf) 0v 100v 200v 300v 15 25 35 45 55 65 75 0.1 1 10 100 frequency (khz) temperasture ( o c) 0v 10 0 v 200v 300v 15 25 35 45 55 65 75 0.1 1 10 100 frequency (khz) temperature ( o c) figure 30. ir2213 vs. freque ncy (irfbc40) r gate =15 , v cc =15v figure 31. ir213 vs . frequency (irfbc50) r gate =10 , v cc =15v
ir2213( s ) & (pbf) www.irf.com 13 16-lead soic (wide body) 01 6015 01-3014 03 (ms-013aa) 01-6010 01-3002 03 (ms-001ac) 14-lead pdip case outlines
14 www.irf.com ir2213( s ) & (pbf) carrier tape dimension for 16soicw code min max min max a 11.90 12.10 0.468 0.476 b 3.90 4.10 0.153 0.161 c 15.70 16.30 0.618 0.641 d 7.40 7.60 0.291 0.299 e 10.80 11.00 0.425 0.433 f 10.60 10.80 0.417 0.425 g 1.50 n/a 0.059 n/a h 1.50 1.60 0.059 0.062 metric imperial reel dimensions for 16soicw code min max min max a 329.60 330.25 12.976 13.001 b 20.95 21.45 0.824 0.844 c 12.80 13.20 0.503 0.519 d 1.95 2.45 0.767 0.096 e 98.00 102.00 3.858 4.015 f n/a 22.40 n/a 0.881 g 18.50 21.10 0.728 0.830 h 16.40 18.40 0.645 0.724 metric imperial e f a c d g a b h note : controlling dimension in mm loaded tape feed direction a h f e g d b c tape & reel 16-lead soic
ir2213( s ) & (pbf) www.irf.com 15 leadfree part 14-lead pdip ir2213 order ir2213pbf 16-lead soic ir2213s order ir2213spbf 16-lead soic tape & reel order IR2213STRPBF order information leadfree part marking information lead free released non-lead free released part number date code irxxxxxx yww? ?xxxx pin 1 identifier ir logo lot code (prod mode - 4 digit spn code) assembly site code per scop 200-002 p ? marking code thisproduct has been designed and qualified for the industrial market. qualification standards can be found on ir?s web site http://www.irf.com data and specifications subject to change without notice. ir world headquarters: 233 kansas st., el segundo, california 90245 tel: (310) 252-7105 1/24/2007 basic part (non-lead free) 14-lead pdip ir2213 order ir2213 16-lead soic ir2213s order ir2213s 16-lead soic tape & reel order ir2213str

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